HPC coprocessor IP development for FPGA based coprocessor board
Kersig is very familiar with offloading computationally intensive calculations to HPC FPGA based coprocessor boards by:
- Identifying the bottleneck in a SW signal processing flow
- Developing highly customized HW IPs of the most computationally critical blocks
- Replace the SW critical blocks by their HW optimized version
Processing speed gains are typically several orders of magnitude for the offloaded processing.
If your application suffers from computational bottlenecks, we can surely help you.